1. Field of the Invention
The present invention relates to a method of and an apparatus for interfacing semiconductor devices that transfer data therebetween.
2. Description of the Related Art
A conventional method of and apparatus for interfacing semiconductor devices for transferring data therebetween will be described below with reference to FIGS. 1(a), 1(b), and 2 of the accompanying drawings.
As shown in FIG. 1(a), a master device 501 and a slave device 502 have respective interface circuits I/O for transmitting and receiving a data signal DT. The interface circuits I/O of the master device 501 and the slave device 502 are connected to each other by a bus 505 which carries the data signal DT. As shown in FIG. 1(b), the data signal DT is transmitted in synchronism with a clock signal Clk that is supplied from a clock generator 503 to the master device 501 and the slave device 502.
The master device 501 can access a plurality of slave devices. A slave device to be accessed is selected by a chip select signal CS that is issued from a decoder 504. The decoder 504 generates the chip select signal CS by decoding an address signal that is issued from the master device 501. The bus 505 is connected to and shared by the master device 501 and the plurality of slave devices.
In recent years, interface circuits have been required to meet requirements for high-speed data transfer. There has been proposed an interface circuit for transmitting and receiving a data signal by reducing the amplitude of the data signal to 1 V or less, for example.
If the amplitude of the transmitted data signal DT is reduced excessively, the receiving device is unable to recognize the data signal. Therefore, it is preferable to set the amplitude of the transmitted data signal DT to the minimum value that can be recognized by the receiving device.
One technique for setting the amplitude of a data signal to a desired value is disclosed in Japanese laid-open patent, publication No. 90-152321, for example. This publication proposes an output circuit capable of setting the amplitude of an output serial signal to a desired value, and describes a process of reducing the amplitude of the output signal for reducing noise such as high-frequency noise.
Specifically, the disclosed output circuit has a plurality of push-pull transistors, a plurality of resistors for establishing higher and lower potentials for the push-pull transistor, a plurality of transistors for selecting the resistors, and a plurality of registers for controlling the turning-on and -off of the transistors. The transistors are turned on or off according to amplitude data written in the registers. The output circuit outputs a serial signal at a potential that is determined by a voltage dividing ratio of the resistors which are selected when the transistors are turned on.
If the disclosed arrangement is applied to the interfacing apparatus shown in FIGS. 1(a) and 1(b), then an interface circuit as shown in FIG. 2 of the accompanying drawings is produced.
As shown in FIG. 2, a conventional interface circuit I/O comprises first and second registers 600, 601 for holding amplitude data to establish an amplitude of a data signal DT to be transmitted to a bus 505, I/O circuits 604 for outputting a data signal DT of a desired amplitude based on the amplitude data held by the first and second registers 600, 601, and an AND gate 603 for ANDing a chip select signal CS and a clock signal Clk. There are as many I/O circuits 604 as the number of bits of the bus 505.
Each of the I/O circuits 604 comprises a pair of push-pull transistors Q64, Q65 whose gates and drains are connected in common, a resistor R64 connected parallel between the source and drain of the push-pull transistor Q64, a resistor R65 connected parallel between the source and drain of the push-pull transistor Q65, resistors R61, R62, R63 having ends connected to the source of the push-pull transistor Q64, a transistor Q61 having a drain connected to the other end of the resistor R61 and a source connected to a voltage source Vdd, a transistor Q62 having a drain connected to the other end of the resistor R62 and a source connected to the voltage source Vdd, a transistor Q63 having a drain connected to the other end of the resistor R63 and a source connected to the voltage source Vdd, resistors R66, R67, R68 having ends connected to the source of the push-pull transistor Q65, a transistor Q66 having a drain connected to the other end of the resistor R66 and a source connected to a ground potential GND, a transistor Q67 having a drain connected to the other end of the resistor R67 and a source connected to the ground potential GND, a transistor Q68 having a drain connected to the other end of the resistor R68 and a source connected to the ground potential GND, and a flip-flop 602 for reading data on the bus 505 into the device in synchronism with an output signal from the AND gate 603.
The transistors Q61.about.Q63 have respective gates connected to output terminals of the first register 600, and the transistors Q66.about.Q68 have respective gates connected to output terminals of the second register 601. The first and second registers 600, 601 supply amplitude data to the I/O circuits 604, which are provided equal in number to the number N of bits of the bus 505.
The first register 600 holds amplitude data of a high potential (H level) for a data signal DT to be transmitted to the bus 505, and the transistors Q61.about.Q63 are turned on and off according to the amplitude data outputted from the first register 600. The second register 601 holds amplitude data of a low potential (L level) for a data signal DT to be transmitted to the bus 505, and the transistors Q66.about.Q68 are turned on and off according to the amplitude data outputted from the second register 601.
Since the transistors Q64, Q65 are push-pull transistors, when one of the transistors Q64, Q65 is turned on, the other is turned off. When the transistor Q64 is turned on and the transistor Q65 is turned off, the interface circuit outputs a data signal DT having an H level. When the transistor Q64 is turned off and the transistor Q65 is turned on, the interface circuit outputs a data signal DT having an L level.
For example, if the first and second registers 600, 601 hold amplitude data for turning on the transistors Q61, Q66 only, then, assuming that the resistances of the transistors Q61, Q66 as they are turned on are ignored, the potentials of the H level (VOH) and the L level (VOL) are determined according to a voltage dividing ratio of the resistors R61, R64, R65, R66 as follows: EQU VOH=[(R65+R66)/(R61+R65+R66)].times.Vdd (1) EQU VOL=[R66/(R61+R64+R66)].times.Vdd (2)
By changing the amplitude data outputted from the first and second registers 600, 601, the potentials of the H level (VOH) and the L level (VOL) can be set to a value determined according to a voltage dividing ratio of the combined resistance of the resistors R61.about.R63, the resistors R64, R65 and the combined resistance of the resistors R66.about.R68.
Therefore, the amplitude of the data signal DT outputted from the I/O circuit 604 can be changed by controlling the turning-on and -off of the transistors Q61.about.Q63 and the transistors Q66.about.Q68 by changing the amplitude data outputted from the first and second registers 600, 601.
FIG. 2 shows only the interface circuit of the slave device 502 shown in FIG. 1. However, the master device 501 shown in FIG. 1 may have the same interface circuit.
A process of optimizing the amplitude of the data signal DT outputted from the interface circuit shown in FIG. 2 will be described below.
(1) First, the master device 501 writes amplitude data into its own first and second registers so as to be able to transmit a data signal having a predetermined optimum amplitude.
(2) Then, the master device 501 transmits a command with the amplitude established in the above step (1) to the slave device 502, thus writing the amplitude data into the first and second registers 600, 601 of the slave device 502.
(3) After having received the command, the slave device 502 transmits, to the master device 501, arbitrary data with an amplitude which is represented by the amplitude data that have been received together with the command. The master device 501 ascertains whether it can recognize the received data or not.
(4) If the master device 501 is unable to recognize the received data, then the master device 501 transmits a command again to the slave device 502, together with amplitude data different from that transmitted in the step (2).
(5) After having received the command, the slave device 502 transmits, to the master device 501, arbitrary data with an amplitude which is represented by the amplitude data that have been received together with the command. The master device 501 ascertains whether it can recognize the received data or not.
(6) The steps (2).about.(5) are repeated until the master device 501 can recognize the received data for thereby adjusting the amplitude of the data signal DT outputted from the slave device 502. The above process is carried out by a controller (not shown) which each of the master device 501 and the slave device 502 has.
The above conventional interface device has been disadvantageous in that if the amplitude of a command that is initially transmitted from the master device 501 to the slave device 502 is inappropriate, then since the slave device 502 fails to recognize the command from the master device 501, it is impossible to establish an amplitude of a data signal DT.